1. Field of the Invention
The present invention relates to a field effect transistor and a method of manufacturing the transistor. More particularly, the present invention relates to a field effect transistor having a drain that is protruded from a substrate, and a method for forming the transistor.
2. Description of the Related Art
In general, semiconductor transistors may be categorized as bipolar junction transistors (BJT) or field effect transistors (FET).
The BJT has electrons and holes as charge carriers. The electron and the hole carry charges in a single transistor. Thus, regardless of whether the transistor is an NPN transistor or a PNP transistor, the charge carrier in the BJT is the electron and the hole.
On the contrary, the FET has only a single charge carrier. The charge carrier is an electron in an N type FET and is a hole in a P type FET. The FET can be a metal-oxide-semiconductor FET (MOSFET) that is widely employed in semiconductor devices.
The MOSFET can be a complementary MOS (CMOS). The CMOS is used in most digital logic circuits. The CMOS has a low operation voltage. Accordingly, although a low voltage is applied to the CMOS, the CMOS may be normally operated. However, when a high voltage is applied to the CMOS, the CMOS may be abnormally operated. As a result, since the CMOS has a low breakdown voltage, the CMOS to which the high voltage is applied may malfunction.
Generally, a high-voltage transistor has a rectifying function and a switching function. To evaluate the functions of the high-voltage transistor, a breakdown voltage and a resistance in the high-voltage transistor are considered as important factors.
The operation voltage of the transistor is determined in accordance with the breakdown voltage. A high breakdown voltage is required for performing the rectifying and the switching functions of the high-voltage transistor when a high voltage is applied to the high-voltage transistor.
A breakdown generated in a semiconductor device is mainly an avalanche breakdown. The avalanche breakdown is caused by an electron-hole pair (EHP). The EHP is generated due to a collision of the charge carrier that receives energy generated by a strong electric field with a molecule for forming a crystalline structure of the semiconductor device. The strong electric field is applied to a depletion region. When the electron or the hole as the charge carrier moves in the depletion region, the electric field applied to the depletion region provides kinetic energy to the charge carrier so that the charge carrier collides with the molecule, thereby losing the kinetic energy. The EHP is then generated from the molecule. This mechanism continuously occurs to generate the avalanche breakdown in the semiconductor device. Thus, when the breakdown is generated, a great amount of current flows through a channel region of the transistor. As a result, the amount of the current varies remarkably in accordance with a tiny increase of voltage so that the semiconductor device may be uncontrollable.
Another breakdown is a Zener breakdown caused by tunneling. The Zener breakdown is generated in a PN junction doped with impurities at a high-concentration. A conduction band of an N type semiconductor device and a valence band of a P type semiconductor device overlap with each other, thereby generating the Zener breakdown. When a concentration profile of the PN junction quickly increases, the Zener breakdown is also generated. Accordingly, when the semiconductor device is doped with impurities at a high-concentration, Zener breakdown is generated before generating the avalanche breakdown. To prevent the occurrence of the Zener breakdown that is generated under a voltage that is relatively low compared to that causing the avalanche breakdown, a region doped with impurities at a low-concentration is required in source/drain regions of the transistor.
In order that the transistor may function as a switch, the channel has a low resistance when the transistor is turned-on, and the channel has a high resistance when the transistor is turned-off. In an ideal transistor, the resistance of the channel is about zero when the transistor is turned-on, and is infinite when the transistor is turned-off. However, in a real transistor, the channel has a resistance in the turned-on or the turned-off state. In particular, the non-infinite resistance of the transistor in the turned-off state causes a leakage current of the transistor. Further, a high resistance of the channel decreases a transmission efficiency of a signal through the channel.
Accordingly, the transistor has a high breakdown voltage and a low resistance to be operated at a high voltage. However, the resistance and the breakdown voltage have a trade-off relation that characteristics of the resistance are degraded when characteristics of the breakdown voltage are improved, and vice versa.
Many transistors are suggested for improving the characteristics of the resistance and the breakdown voltage.
A conventional transistor is formed so as to have a lightly doped drain (LDD) structure. Source/drain regions doped with impurities at a low-concentration are formed to surround source/drain regions doped with impurities at a high-concentration, respectively, to provide a high breakdown voltage to the transistor. The source region doped with impurities at a low-concentration is extended under a gate oxide layer. The drain region doped with impurities at a low-concentration is extended under a portion of the gate oxide layer that is disposed adjacent to the drain region doped impurities at a high-concentration impurity. A length of a channel region is shortened in the structure described above, thereby reducing the resistance of the transistor. Further, the source/drain regions doped with impurities at a low-concentration, which intersect each other at both sides of the gate oxide layer, prevent a hot-carrier injection generated in the channel region adjacent to the drain region doped with impurities at a high-concentration. Particularly, the source/drain regions doped with impurities at a low-concentration increase a width between the source/drain regions doped with impurities at a high-concentration so that the transistor has a high breakdown voltage.
Another conventional transistor has a lateral double-diffused MOS (LDMOS). The LDMOS has improved resistance and breakdown voltage characteristics. The LDMOS is also normally operated by an input signal having a high frequency. Further, since the LDMOS may be fabricated by processes for manufacturing standard CMOS and by additional processes, the LDMOS is employed in conventional process lines for manufacturing the standard CMOS. The LDMOS has a very short channel length so that the transistor has improved high frequency and resistance characteristics. To improve the breakdown voltage characteristic, an interval between the source region and the drain region that are doped with impurities at a high-concentration is widened. Thus, the drain region is needed to have a wide lightly doped region. A structural feature of the LDMOS is that the transistor has a channel region separated from a drift region, whereas other transistors have the channel and drift regions into one combined region. The drift region for maintaining the high voltage that is applied to the drain region is doped with impurities at a low-concentration to a great extent. The channel region through which the charge carrier passes has a very short length for suppressing the occurrence of the EHP. Additionally, the LDMOS has a base and a base contact for capturing an electron or a hole that is generated by moving the charge carrier.
The above-mentioned conventional transistors are required to have the wide low-concentration impurity region so that the area occupied by transistors in a semiconductor device is enlarged. Numbers of semiconductor devices on a wafer, that is, a net die, are reduced. Further, a photoresist pattern may be mis-aligned in an ion implantation process for forming the source/drain regions so that characteristics of a semiconductor device may be greatly changed. As a result, guaranteeing a process margin may be difficult.